This invention relates to programmable logic devices, and more particularly it relates to architecture for a high-density programmable logic device, with flexible local connections and local controls, as well as fast multiplexer based global interconnections.
Most medium and high-density complex programmable logic devices have evolved from simple programmable logic devices (SPLD). They feature a structure of logic blocks connected by a programmable global interconnection facility that allows information to be exchanged between the logic blocks. The logic block, which is functionally like a simple programmable logic device, normally comprise a PLA (usually an AND array drives an OR array) and a number of macrocells. The introduction of the global interconnection allows the implementation of logic more complex than that which can be fitted in an SPLD. This is achieved by mapping complex logic into different logic blocks, and connecting the blocks, through the programmable global interconnection, according to the application logic function. The main features of these devices, such as speed performance, density, logic flexibility, effective utilization of resources, and software complexity required for mapping an application design, rely heavily on logic block structure, global interconnection structure, and how they are scheduled and connected to balance the conflicting factors.
Some programmable logic devices, especially medium density complex programmable logic devices, and high-density programmable logic devices with low performance, utilize a full-cross point global programmable interconnect array (PIA) to interconnect the logic blocks. All global signals are typically brought in to the programmable interconnect array and the input signals from each logic block are generated in the programmable interconnect array. Each input signal for the logic block is essentially a function of all global signal sources. This global connectivity approach provides 100% connectivity for all global signals, and greatly alleviates software complexity and facilitates signal routeability.
However, to meet ever increasing technological demands, programmable logic devices have been constantly increasing in both size and complexity. In particular, to achieve higher logic density, more logic blocks, and thus more global signals, have been incorporated into programmable logic devices. This results in an almost exponential increase in the size of the programmable interconnect array. On the other hand, a major speed limitation of the programmable logic device is capacitive loading in the elements of the programmable interconnect array. Increasing the size of the programmable interconnect array leads to an undesirable reduction in speed. Furthermore, since the programmable interconnect array is monolithic, the number of input signals needed is usually significantly smaller than the full capability of the device. As a result, most of the signal paths remain unutilized. This represents a significant wastage of resources. As the disadvantages of silicon die size increase, speed degradation, and wasted resources make the programmable interconnect array approach no longer suitable for programmable logic devices with ever increasing density and complexity.
An alternative to the programmable interconnect array in high-density complex programmable logic devices is the multiplexer based, sparse global interconnect matrix structure. This approach focuses on optimized routeability, speed, and die size in a more intelligent manner. In this structure, the programmable elements in the programmable interconnect array are replaced by a group of multiplexers in a new programmable global interconnect multiplex matrix. Only selected global signals are connected to the inputs of the multiplexers, in a predetermined optimized pattern, and the outputs of the multiplexers are connected to the inputs of logic blocks. This structure has four important parameters: routeability (chances for every global signal to be routed to the inputs of a logic block), number of global signals, number of logic block inputs, and multiplexer size. These parameters have a relationship described by the following equation: Routeability=(multiplexer size.times.number of logic block inputs)/number of global signals. With the increase in density of the device, the number of global signals is consequently increased, while keeping the number of logic block inputs unchanged, the multiplexer size is necessarily increased to maintain the routeability. Unfortunately, a larger multiplexer structure results in slower performance and bigger die sizes.
Another problem with some higher-density programmable logic devices using the programmable global interconnect multiplex matrix is that, in order to have a simplified timing model and timing characteristics, all the feedbacks from a logic block are fed to the global interconnect multiplex matrix as global signals, though some of them are merely fed back to the local logic block. The purpose of the global interconnect multiplex matrix is to intelligently offer interconnects, between logic blocks from a group of limited resources. If the local signals are fed back to local logic blocks through some of these global resources, more outputs from the global interconnect multiplex matrix are needed. This will also result in a greater number of muliplexers and bigger die sizes.
In view of the foregoing, it would be desirable to be able to provide a high-density programmable logic device architecture that utilizes the multiplexer based global interconnections instead of the programmable interconnect array.
It would further be desirable to be able to provide a high density programmable logic device architecture, in which the structure of the logic block is flexible enough to handle all the local signals, and in which only global signals to other logic blocks utilize multiplexer based global interconnection resources.
It would also be desirable to be able to provide a high-density programmable logic device architecture with balanced routeability and speed.